1. Field of the Invention
The invention relates generally to the field of microelectronic fabrication. More particularly, the invention relates to a technique of optimizing the throughput, reliability, and quality of microelectronic fabrication by synchronizing the individual processing and transportation mechanisms within a fabrication system.
2. Discussion of the Related Art
In the process of manufacturing a semiconductor device such as an integrated circuit, numerous steps of micro-fabrication are performed to form a device. These steps are performed serially on the individual items of manufacture in individual modules; the items of manufacture are transferred between modules by transport mechanisms such as robots. In order to achieve desirable throughput, reliability, and fabrication quality, several conditions must be met:
1) The delivery and removal of the substrate to and from the process modules, as well as the transportation of the wafer between modules, must be accomplished in a timely manner. This timely delivery and removal of substrate is achieved when the flow of substrate is maintained in a periodic and synchronized manner. If periodicity and synchronization are not maintained, the process results will be inconsistent from substrate to substrate, and the expected throughput may be reduced.
2) It is desirable to transport the substrate in similar process flow paths to avoid inconsistency in process results due to variations in the process history of the substrates.
3) It is imperative to ensure that the articles of manufacture do not spend any pre-process or post-process time idling in modules where critical processes are performed. The addition of pre-process or post-process time in these modules degrades not only the throughput but also the process results. For example, in an IC fabrication system, if a substrate is not immediately transferred from the spin coat module to a bake module to thermally cure a photo-resist film layer, the resulting film thickness will be unpredictable. If it is impossible to totally eliminate pre-process and/or post-process times, they should be rendered as brief as possible, and any variations in these times cannot be allowed.
The inability to meet any or all of the above conditions come from the failure to resolve transport conflicts. Conflicts are situations wherein separate modules demand a robot within a time span insufficient for the robot to service these modules
One conventional solution to the concerns listed above is the addition of extra process modules and transportation resources. However, the size limitations and geometrical constraints of a track system limit the possibility of resolving the above difficulties by adding additional process modules or transportation resources.
The addition of dedicated transfer arms to transfer substrates between adjacent modules (hereinafter called Inter Bay Transfer Arms, or IBTAs) is another method used to improve throughput and eliminate some of the pre-process and/or post-process times. However, the addition of IBTAs also has serious drawbacks. Dedicated transfer arms complicate the tool and increase its cost, constrain the position of the modules, and cannot be used everywhere in the tool. As a result, the tasks of managing the substrate flow in the track system while maintaining both high throughput and quality and resolving all transport conflicts become unmanageable.
Another conventional solution is to assign a set of substrate transport priority rules. Prior to any robot move, the control system, also referred to as the software scheduler, verifies the status of substrates in different modules and makes transfer priority decisions based on these rules. However, to achieve high throughputs, the scheduler may generate undesirable, unpredictable and variable pre-process and post-process times in critical modules, and the substrates may also be forced to follow different flow paths to complete their process cycle.
A substrate processing system may further include lithographic projection apparatus that can be used in the manufacture of integrated circuits (ICs). In such a case, the patterning means may generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (comprising one or more dies) on a substrate that has been coated with a layer of radiation-sensitive material. In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In some current apparatus, employing patterning by a mask on a mask table, a distinction can be made between two different types of machine. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion at once using what is commonly referred to as a wafer stepper. In an alternative apparatus, which is commonly referred to as a stop-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the xe2x80x9cscanningxe2x80x9d direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since the projection system will generally have a magnification factor M (generally less than 1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792 which is incorporated herein by reference in its entirety.
There is a continuing desire in the semiconductor industry to be able to manufacture ICs with ever higher component densities and hence smaller feature size. To image smaller features in a lithographic projection apparatus it is necessary to use projection radiation of shorter wavelength. A number of different type of projection radiation have been proposed, including Extreme Ultraviolet (EUV) in the 10-20 nm range, electron beams, ion beams and other charged particle fluxes. These types of radiation beam share the requirement that the beam path, including the mask, substrate and optical components, be kept in a high vacuum. This is to prevent absorption and/or scattering of the beam and a total pressure of less than about 10xe2x88x926 millibar is necessary. Optical elements for EUV radiation can be spoiled by the deposition of carbon layers on their surface which imposes the additional requirement that hydrocarbon partial pressures must be kept below 10xe2x88x928 or 10xe2x88x929 millibar.
Lithographic apparatus may employ various types of projection radiation, non-limiting examples of which include ultra-violet light (xe2x80x9cUVxe2x80x9d) radiation (e.g., with a wavelength of 365 nm, 248 nm, 193 nm, 157 nm or 126 nm), EUV, X-rays, ion beams or electron beams. Depending on the type of radiation used and the particular design requirements of the apparatus, it may comprise a projection system having refractive, reflective or catadioptric components, and comprise vitreous elements, grazing-incidence mirrors, selective multi-layer coatings, magnetic and/or electrostatic field lenses, etc; for simplicity, such components may be loosely referred to in this text, either singly or collectively, as a xe2x80x9clens.xe2x80x9d
In a manufacturing process using such a lithographic projection apparatus, a pattern in a mask is imaged onto a substrate or silicon wafer which is at least partially covered by a layer of radiation-sensitive material such as resist. Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate or wafer. These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes may be obtained, for example, from the book xe2x80x9cMicrochip Fabrication: A Practical Guide to Semiconductor Processingxe2x80x9d, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997 ISBN 0-07-067250-4.
Heretofore, the semiconductor processing requirements of conflict resolution, synchronization, quality, and path consistency referred to above have not been fully met. What is needed is a solution that simultaneously addresses all of these requirements.
A primary goal of the invention is to provide a synchronized substrate-transporting algorithm that resolves any possible flow conflicts and thereby improves the performance and the throughput of a track system.
Another primary goal of the invention is to provide an algorithm that determines the optimal allocation of transportation resources for balancing the load amongst transport mechanisms.
Another primary goal of the invention is to enable flexible synchronization of the fabrication system, ensuring that substrate processing and transportation occur at regular, predictable intervals without diminishing the throughput.
In accordance with these goals, there is a particular need for an algorithm that synchronizes the fabrication system, so that each process or substrate transportation always occurs at precise point in the interval. Thus, it is rendered possible to simultaneously satisfy the above-discussed requirements of conflict resolution, synchronization, optimized throughput, and wafer quality, which, in the case of the prior art, are mutually contradicting and are not simultaneously satisfied.
A first aspect of the invention is implemented in an embodiment that is based on an algebraic transformation. A second aspect of the invention is implemented in an embodiment that is based on a genetic algorithm.
With respect to yet another aspect of the invention, a clustered wafer track and lithography system is provided. The benefits of the invention as described herein extend beyond a wafer track alone and are applicable to a combined wafer track and stepper apparatus. The synchronization and optimization of processing substrates in accordance with the invention efficiently achieves high and reliable throughput that can be measured and observed on a systemwide level.
These, and other, goals and aspects of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the invention without departing from the spirit thereof, and the invention includes all such modifications.